Many battery-powered portable electronic devices, such as laptop computers, Portable Digital Assistants, digital cameras, cell phones and the like, require memory devices that provide large storage capacity and low power consumption. One type of memory device that is well-suited to use in such portable devices is flash memory, which is a type of semiconductor memory that provides a relatively large nonvolatile storage capacity for data. The nonvolatile nature of the storage means that the flash memory does not require power to maintain the data, as will be appreciated by those skilled in the art.
A typical flash memory comprises a memory-cell array having an array of memory cells arranged in rows and columns and grouped into blocks. FIG. 1 illustrates a conventional flash memory cell 100 formed by a field effect transistor including a source 102 and drain 104 formed in a substrate 106, with a channel 108 being defined between the source and drain. Each of the memory cells 100 further includes a control gate 110 and a floating gate 112 formed over the channel 108 and isolated from the channel and from each other by isolation layers 114. In the memory-cell array, each memory cell 100 in a given row has its control gate 110 coupled to a corresponding word line WL and each memory cell in a given column has its drain 104 coupled to a corresponding bit line BL. The sources 102 of each memory cell 100 in a given block are coupled together to allow all cells in the block to be simultaneously erased, as will be appreciated by those skilled in the art.
The memory cell 100 is charged or programmed by applying appropriate voltages to the source 102, drain 104, and control gate 110 and thereby injecting electrons e−from the drain 104 and channel 108 through the isolation layer 114 and onto the floating gate 112. Similarly, to erase the memory cell 100, appropriate voltages are applied to the source 102, drain 104, and control gate 110 to remove electrons e−through the isolation layer 114 to the source 102 and channel 108. The presence or absence of charge on the control gate 112 adjusts a threshold voltage of the memory cell 100 and in this way stores data in the memory cell. When charge is stored on the floating gate 112, the memory cell 100 does not turn ON when an access voltage is applied through the word line WL to the control gate 110, and when no charge is stored on the floating gate the cell turns ON in response to the access voltage. In this way, the memory cell 100 stores data having a first logic state when the cell turns ON and a second logic state when the cells does not turn ON.
In a conventional flash memory, a row driver is coupled to each word line WL in the memory-cell array and operates to access memory cells 100 in the corresponding row in response to activation signals. FIG. 2 illustrates a conventional row driver 200 including a PMOS drive transistor 202 and NMOS drive transistor 204 coupled in series, with a supply voltage VX and a first reference voltage VXGND being applied to the sources of the PMOS drive transistor and NMOS drive transistor, respectively. The interconnection of the drains of the transistors 202 and 204 define a node 206 that is coupled to a corresponding word line WL. A second PMOS transistor 208 and NMOS transistor 210 are coupled in series, with the supply voltage VX and a second reference voltage XPDACOM being applied to the sources of the transistors, respectively. The interconnection of the drains of the transistors 208, 210 defines a node 212 that is coupled to the gates of the drive transistors 202 and 204. The transistor 210 receives a first activation signal XPDA and the PMOS transistor 208 receives a second activation signal VXDECEN#. Typically, the first and second reference voltage VXGND and XPDACOM are ground while the supply voltage VX is 5 volts.
In operation, the row driver 200 operates in a select mode to activate memory cells 100 (not shown in FIG. 2) coupled to the word line WL and operates in a deselect mode to turn OFF or deactivate memory cells coupled to the word line, as will now be explained in more detail. In the select mode, the VXDECEN# and XPDA signals are high, turning OFF the PMOS transistor 208 and turning ON the NMOS transistor 210, respectively. The node 212 is driven low through the transistor 210, turning OFF the drive transistor 204 and turning ON the drive transistor 202 which, in turn, drives the word line WL high to approximately the supply voltage VX through the transistor 202. At this point, the memory cells 100 (see FIG. 1) coupled to the word line WL either turn ON or remain OFF, depending on whether a memory cell has been programmed or erased (i.e., depending on the data stored in the cell). In this way, address decode circuitry (not shown) in the flash memory containing the row driver 200 activates the XPDA signal corresponding to the row of memory cells to be accessed. In response to the activated XPDA signal, the corresponding row driver 200 drives the word line WL high to thereby access the memory cells 100 in the corresponding row.
In the deselect mode, the VXDECEN# and XPDA signals are low, turning ON the PMOS transistor 208 and turning OFF the NMOS transistor 201, respectively. The node 212 is driven high through the transistor 208, turning OFF the drive transistor 202 and turning ON the drive transistor 204 which, in turn, drives the word line WL low to approximately ground through the transistor 204. At this point, all the memory cells 100 coupled to the word line WL are turned OFF, regardless of whether a cell has been programmed or erased. Each row driver 200 operates in the deselect mode when the corresponding row of memory cells 100 is not being accessed.
During normal operation of the flash memory, each row driver 200 alternately operates in either the select or deselect mode, depending on whether the corresponding row of memory cells 100 is being accessed or not. The normal mode includes operation of the flash memory during data transfers and when memory cells are being programmed and erased. All the row drivers 200 operate in the deselect mode during a sleep or power-savings mode of operation of the flash memory. As previously mentioned, many battery-powered portable electronic devices utilize flash memory, and to reduce the power consumption and thereby extend the battery life in such devices, the flash memory is typically placed in the power-savings mode when the flash memory is not being used. When in the power-savings mode, the row driver 200 operates as previously described to drive the word line WL low and deactivate all the corresponding memory cells 100.
When a flash memory is operating in the power-savings mode, the memory will at some point be activated to commence data transfer operations in the normal mode. For example, in a portable device the flash memory may be operate in the power-savings mode when the device is turned OFF, and be activated in response to a user turning ON the device. The time required to switch from the power-savings mode to the active mode is ideally minimized so that a user does not experience a delay due to the flash memory changing modes of operation. Thus, the flash memory should be able to begin transferring data to and from the memory cells 100 as soon as possible after termination of the power-savings mode. As a result, during the power-savings mode, a charge pump (not shown) that develops the supply voltage VX continues operating to provide the supply voltage VX to the row drivers 200. In this way, when the power-savings mode is terminated, a selected row driver 200 may activate the corresponding word line WL more quickly than if the driver needed to wait for the charge pump to generate the supply voltage VX having the required magnitude.
Ideally, operation of the charge pump during the power-savings mode consumes no power since all the row drivers 200 are driving the word lines WL low and the PMOS drive transistors 202 are turned OFF, as previously described. More specifically, during the power-savings mode, the VXDECEN# and XPDA signals are low, driving the node 212 high through the transistor 208 and thereby turning OFF the PMOS drive transistor 202. Due to the voltages applied to the source, drain, and gate of the PMOS drive transistor 202, however, a gate induced drain leakage (GIDL) current IGIDL flows through the PMOS drive transistor, as will be appreciated by those skilled in the art. FIG. 3 is a simplified cross-sectional view of the PMOS drive transistor 202 illustrating the IGIDL current through the transistor in this situation. A high electric field is developed in an area 300 where the gate 302 overlaps the drain 304 of the PMOS drive transistor 202. The high electric field is due to the supply voltage VX being applied to the gate 302 and ground being applied to the drain 304 and generates the IGIDL current. The concept of a gate induced drain leakage current is understood by those skilled in the art, and thus, for the sake of brevity, will not be discussed in more detail.
During the power-savings mode, the NMOS drive transistor 204 is turned ON in response to the node 212 (FIG. 2) being driven high through the transistor 208. As a result, the IGIDL current flows through the PMOS drive transistor 202 and through the NMOS drive transistor 204 to ground in each row driver 200. While the IGIDL current through an individual PMOS transistor 202 in a single row driver 200 is small, the summation of the IGIDL currents through all the row drivers may be relatively large, and can cause the charge pump developing the supply voltage VX to consume a significant amount of power during the power-savings mode of operation. The total current consumed by the charge pump will actually be substantially greater than the summation of the leakage currents IGIDL through the row drivers 200 due to operating inefficiencies of the charge pump, as will be appreciated by those skilled in the art.
There is a need for a row driver having a reduced leakage current to lower power consumption during a power-savings mode of operation of a flash memory or other type of memory device containing the row driver.